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1/34 june 2004 stv0056a satellite sound and video processor rev. 2 sound two independent sound demodulators pll demodulation with 5-10mhz frequency synthesis programmable fm demodulator bandwidth accomodating fm deviations from 30khz till 400khz programmable 50/75s, j17 or no deemphasis wegener panda system two auxiliary audio inputs and outputs gain controlled and muteable audio outputs high impedance mode audio outputs for twin tuner applications video composite video 6-bit 0 to 12.7db gain control composite video selectable inverter two selectable video de-emphasis networks 6 x 3 videomatrix black level adjustable output for on-board videocrypt decoder high impedance mode video outputs for twin tuner applications miscellaneous 22khz tone generation for lnb control i 2 c bus control chip addresses = 06 hex or 46 hex low power stand-by mode with active audio and video matrixes figure 1. package figure 2. pin connections shrink56 (plastic package) 1 fc r 2 pk in r 3 level rr 4 s1 vid rtn 5 s3 vid rtn 6 vol r 7 s3 vid out 8 s1 vid out 9 s2 vid out 10 vol l 11 s2 vid rtn 12 s2 out l 13 clamp in 14 s2 out l 15 uncl deem 16 videem2/22khz 17 v 12v 18 videem1 19 v gnd 20 b-band in 21 s2 rtn l 22 s2 rtn r 23 fm in 24 s3 rtn l 25 s3 rtn r 26 agc l 27 s3 out l 28 s3 out r a gnd r 56 fc l 55 pk in l 54 level l 53 pk out l 52 pk out r 51 i ref 50 cpump r 49 u75 r 48 det r 47 amplk r 46 a 12v 45 v ref 44 a gnd l 43 agc r 42 amplk l 41 u75 l 40 det l 39 cpump l 38 gnd 5v 37 v dd 36 xtl 35 j17 l 34 j17 r 33 ha 32 sda 31 scl 30 i/o/22khz 29
stv0056a 2/34 description the stv0056a bicmos integrated circuit realiz- es all the necessary signal processing from the tuner to the audio/video input and output connec- tors regardless of the satellite system. table 1. pin assignment pin number name function 1 fc r audio roll-off right 2 pk in r noise reduction peak detector input right 3 level r noise reduction level right 4 s1 vid rtn tv-scart 1 video return 5 s3 vid rtn decoder-scart video return 6 vol r volume controlled audio out right 7 s3 vid out decoder-scart video output 8 s1 vid out tv-scart 1 video output 9 s2 vid out vcr-scart 2 video output 10 vol l volume controlled audio out left 11 s2 vid rtn vcr-scart 2 video return 12 s2 out l fixed level audio output left (to vcr) 13 clamp in sync-tip clamp input 14 s2 out r fixed level audio output right (to vcr) 15 uncl deem unclamped de-emphasized video output 16 videem2/22khz video de-emphasis 2 or 22khz output 17 v 12v video 12v supply 18 videem1 video de-emphasis 1 19 v gnd video ground 20 b-band in base band input 21 s2 rtn l auxiliary audio return left (from vcr) 22 s2 rtn r auxiliary audio return right (from vcr) 23 fm in fm demodulator input 24 s3 rtn l auxiliary audio return left (from decoder) 25 s3 rtn r auxiliary audio return right (from decoder) 26 agc l agc peak detector capacitor left 27 s3 out l auxiliary audio output l (to decoder) 28 s3 out r auxiliary audio output r (to decoder) 29 i/o/22khz digital input/o utput or 22khz output 30 scl i 2 c bus clock 31 sda i 2 c bus data 32 ha hardware address
3/34 stv0056a sound detection fmin this is the input to th e two fm demodulators. it feeds two agc amplifiers with a band width of at least 5-10mhz. there is one amplifier for each channel both with the same input. the agc ampli- fiers have a 0db to +40db range. z in = 5k ? , min input = 2mv pp per sub carrier. max input = 500mv pp (max when all inputs are added together, when their phases coincide). agc l, agc r agc amplifiers peak detector capacitor connec- tions. the output current has an attack/decay ratio of 1:32. that is the ramp up current is approximately 5a and decay current is approximately 160a. 11v gives maximum gain. these pins are also driven by a circuit monitoring the voltage on am- plk l and amplk r respectively. amplk l, amplk r the outputs of amplitude detectors left and right. each requires a ca pacitor and a resistor to gnd. the voltage across this is used to decide whether there is a signal being received by the fm detector. the level detector output drives a bit in the detector i 2 c bus control block. amplk l and amplk r dr ive also respectively agc l and agc r. for instance when the voltage 33 j17 r j17 de-emphasis time constant right 34 j17 l j17 de-emphasis time constant left 35 xtl 4/8mhz quartz crystal or clock input 36 v dd 5v digital 5v power supply 37 gnd 5v digital power ground 38 cpump l fm pll charge pump capacitor left 39 det l fm pll filter left 40 u75 l de-emphasis time constant left 41 amplk l amplitude detector capacitor left 42 agc r agc peak detector capacitor right 43 a gnd l audio ground 44 v ref 2.4v reference 45 a 12v audio 12v supply 46 amplk r amplitude detector capacitor left 47 det r fm pll filter right 48 u75 r de-emphasis time constant right 49 cpump r fm pll charge pump capacitor right 50 i ref current reference resistor 51 pk out r noise reduction peak detector output right 52 pk out l noise reduction peak detector output left 53 level l noise reduction level left 54 pk in l noise reduction peak detector input 55 fc l audio roll-off left 56 a gnd r audio ground pin number name function
stv0056a 4/34 on amplkl is > (v ref + 1 v be ) it sinks current to v ref from pin agcl to reduce the agc gain. det l, det r respectively the outputs of the fm phase detector left and right. this is for the connection of an external loop filter for the pll. the output is a push-pull current source. cpump l, cpumpr the output from the frequency synthesizer is a push-pull current source which requires a capaci- tor to ground to derive a voltage to pull the vco to the target frequency. the output is 100a to achieve lock and 2a during lock to provide a tracking time constant of approximately 10hz. v ref this is the audio processor voltage reference used through out the fm/audio section of the chip. as such it is essential that it is well decoupled to ground to reduce as far as possible the risk of crosstalk and noise injectio n. this voltage is de- rived directly from the band gap reference of 2.4v. the v ref output can sink up to 500a in normal operation and 100a when in stand-by. i ref this is a buffered v ref output to an off-chip resis- tor to produce an accurate current reference, with in the chip, for the biasing of amplifiers with current outputs into filters. it is also required for the noise reduction circuit to provide accurate roll-off fre- quencies. this pin should not be decoupled as it would inject current noise. the target current is 50a 2% thus a 47.5k ? 1% is required. a 12v double bonded main power pin for the audio/fm section of the chip. the two bond connections are to the esd and to power the circuit and on chip regulators/references. a gnd l this ground pin is double bonded: 1. to channel left: rf section & vco, 2. to both agc amplifiers, channel left and right audio filter section. a gnd r this ground pin is double bonded: 1. to the volume control, noise reduction system, esd + mux + v ref 2. to channel right: rf section & vco baseband audio processing pk out l, pk out r, pk out the noise reduction control loop peak detector output requires a capacitor to ground from this pin, and a resistor to v ref pin to give some accurate decay time constant. an on chip 5k ? 25% resis- tor and external capacitor give the attack time. pk in l, pk in r or pk in each of these pins is an input to a control loop peak detector and is connected to the output of the off chip control loop band pass filter. level l, levelr respectively the audio left and right signals of the fm demodulators are output to level l and level r pins through an input follower buffer. the off-chip filters driven by these pins must include ac cou- pling to the next stage (pk in l and pk in r pins respectively). fc l, fc r the variable bandwidth transconductance amplifi- er has a current output which is variable depend- ing on the input signal amplitude as defined by the control loop of the noise reduction. the output cur- rent is then dumped into an off-chip capacitor which together with the accurate current reference define the min/max roll off frequencies. a resistor in series with a capacitor is connected to ground from these two pins. j17 l, j17r the external j17 de-emphasis networks for chan- nels left and right. the amplif ier for this f ilter is volt- age input, current output. output with 500mv input will be 55a. to perform j17 de-emphasis with the stv0042, an external circuit is required. u75 l, u75 r external de-emphasis networks for channels left and right. for each channel a capacitor and resis- tor in parallel of 75s time constant are connected between here and v ref to provide 75s de-em- phasis. internally selectable is an internal resistor that can be programmed to be added in parallel thereby converting the network to approx 50s de-empha- sis (see control block map). the value of the inter- nal resistors is 54k ? 30%. the amp lifier for this filter is voltage input, current output; with 500mv input the output will be 55a. vol l, vol r the main audio output from the volume control amplifier the signal to get output signals as high as 2v rms (+12db) on a dc bias of 4.8v. control is from +12db to ?26.75db plus mute with 1.25db steps.this amplifier has short circuit protection and is intended to drive a scart connector di- rectly via ac coupling and meets the standard scart drive requirements. these outputs feature high impedance mode for parallel connection.
5/34 stv0056a s2 out l, s2 outr, s3 out l, s3 out r these audio outputs are sourced directly from the audio mux, and as a result do not include any vol- ume control function. they will output a 1v rms sig- nal biased at 4.8v. they are short circuit protected. these outputs feature high impedance mode for parallel connection and meet scart drive re- quirement. s2 rtn l, s2 rtn r, s3 rtn l, s3 rtn r these pins allow auxiliary audio signals to be con- nected to the audio processor and hence makes use of the on-chip volume control. for additional details please refer to the audio switching table. video processing b-band in ac-coupled video input from a tuner. z in > 10k ? 25%. this drives an on-chip video amplifier. the other input of this amp is ac grounded by being connected to an internal v ref . the video amplifier has selectable gain from 0db to 12.7db in 63 steps and its output signal can be selected normal or inverted. uncl deem de-emphasized still unclamped output. it is also an input of the video matrix. videem1 connected to an external de-emphasis network (for instance 625 lines pal de-emphasis). videem2 / 22khz connected to an external de-emphasis network (for instance 525 lines ntsc or other video de- emphasis). alternatively a precise 22khz tone may be output by i 2 c bus control. clamp in this pin clamps the most negative extreme of the input (the sync tips) to 2.7v dc (or appropriate volt- age). the video at the clamp input is only 1v pp . this clamped video which is de-emphasized, fil- tered and clamped (energy dispersal removed) is normal, negative syncs, video. this signal drives the video matrix input called normal video. it has a weak (1.0a 15%) stable current source pulling the input towards g nd. otherwise the input impedance is very high at dc to 1khz z in > 2m ? . video bandwidth through this is ?1db at 5.5mhz. the clamp input dc restore voltage is then used as a means for getting the correct dc voltage on the scart outputs. s3 vidrtn this input can be driven for instance by the decod- er. this input has a dc restoration clamp on its in- put. the clamp sink current is 1a 15% with the buffer z in > 1m ? . s2 vid rtn, s1 vid rtn external video input 1.0v pp ac coupled 75 ? source impedance. this input has a dc restora- tion clamp on its input. the clamp sink current is 1a 15% with the buffer z in > 1m ? . this signal is an input to the video matrix. s1 vid out, s2 vid out video drivers for scart 1 and scart 2. an ex- ternal emitter follower buffer is required to drive a 150 ? load. the average dc voltage to be 1.5v on the o/p. the signal is video 2.0v pp 5.5mhz bw with sync tip = 1.2v. these pins get signals from the video matrix. the signal selected from the vid- eo matrix for output on this pin is controlled by a control register. this output also feature a high im- pedance mode for parallel connection. s3 vid out this output can drive for instance a decoder. also it is able to pass 10mhz; z out < 75 ? . video on this pin will be 2v pp . the black level of the output video signal can be adjusted through i 2 c bus con- trol to easily interface with on-board videocrypt decoder. this output feature an high impedance mode for parallel connection. v 12v +12v double bonded: esd+guard rings and video circuit power. v gnd doubled bonded.clean vid in gnd. strategically placed video power ground connection to reduce video currents getting into the rest of the circuit. control block gnd 5v the main power ground connection for the control logic, registers, the i 2 c bus interface, synthesizer & watchdog and xtlosc. v dd 5v digital +5v power supply. scl this is the i 2 c bus clock line. clock = dc to 100khz. requires external pull up eg. 10k ? to 5v. sda this is the i 2 c bus data line. requ ires external pull up eg. 10k ? to 5v. i/o / 22khz general purpose input output pin or 22khz output.
stv0056a 6/34 xtl this pin allows for the on -chip oscillator to be ei- ther used with a crystal to ground of 4mhz or 8mhz, or to be driven by an external clock source. the external source can be either 4mhz or 8mhz. a programmable bit in the control block removes a 2 block when the 4mhz option is selected. ha hardware address with internal 135a pull down. chip address is 06 when this pin is grounded and chip address is 46 when connected to v dd . figure 3. general block diagram 22khz to lnb from tuner from tuner to tv, vcr/decoder active in stand-by i 2 c bus interface audio matrix + volume 6 x 3 video matrix b-band video processing fm demodulation 2 channels wegener panda + deemphasis 3 2 2 4 3 from tv, vcr/decoder stv0056a
7/34 stv0056a figure 4. video processing block diagram lpf ntsc pal videem1 videem2/22khz i/o/22khz b-band in clamp in clamp clamp clamp black level adjust s3 vid out s1 vid out to decoder s2 vid out to vcr to tv clamp normal baseband deemphasized decoder return vcr return tv return 13 16 18 15 2 789 20 g 1 29 5 11 4 s3 vid rtn s2 vid rtn s1 vid rtn 22khz tone uncl deem + - + - stv0056a
stv0056a 8/34 figure 5. audio processing block diagram (channel right) figure 6. audio processing block diagram (channel left) audio r pll filter audio decoder out audio decoder return decoder vcr 33 1 2 51 25 28 6db k6 k2 k1 k4 k3 4 a a a b b b c a a b c a b c bc -6db 6db -6db anrs audio deemphasis 47 3 48 14 22 6 tv mono stereo det r s3 out r s3 rtn r s2 out r s2 rtn r vol r pk out r pk in r level r fc r j17 r u75 r stv0056a audio l pll filter audio decoder out audio decoder return decoder vcr 32 55 54 52 24 27 6db k6 k5 k1 k2 k4 k3 4 a a a b b b c a a b c a b c bc -6db 6db -6db anrs audio deemphasis 39 53 40 12 21 10 tv mono stereo det l s3 out l s3 rtn l s2 out l s2 rtn l vol l pk out l pk in l level l fc l j17 l u75 l stv0056a
9/34 stv0056a figure 7. audio switching k4: a anrs input non-scrambled audio b anrs input descrambled audio table 2. anrs selection audio pll dec rtn aux in vol out aux out dec out audio deemphasis + anrs k 1a k 5b k 1b k 1c k 5a k 6c k 5c k 6a k 6b k 2 k 3 a b1 b2 c a a a a no anrs, no de-emphasis no anrs, 50ms no anrs, 75ms no anrs, j17 a b1 b2 c b b b b anrs, no de-emphasis anrs, 50ms anrs, 75ms anrs, j17
stv0056a 10/34 figure 8. fm demodulation block diagram circuit description video section the composite video is firs t set to a standard level by means of a 64 step gain controlled amplifier. in the case that the modulation is negative, an invert- er can be switched in. one of two different external video de-emphasis networks (for instance pal and ntsc) is select- able by an integrated bus controlled switch. then energy dispersal is removed by a sync tip clamping circuit, which is used on all inputs to a video switching matrix, thus making sure that no dc steps occur when switching video sources. the matrix can be used to feed video to and from decoders, vcr?s and tv?s. a bus controlled black leve l adjustment circuit is provided on the decoder output allowing a direct connection to an on-boar d videocrypt decoder. additionally all the video outputs are tristate type (high impedance mode is supported), allowing a simple parallel connections to the scarts (twin tun- er applications). audio section the two audio channels are totally independent except for the possibility given to output on both fm in det r cpump r audio r audio l det l cpump l agc r amplk r v ref v ref 90 0 vco v ref 90 0 vco agc l amplk l agc + + + + + - level detector 1 level detector 2 reg8 b4 watchdog synthesizer sw2 sw4 bias sw1 phase detect fm dev. select. fm dev. select. amp. detect v ref agc + - level detector 1 level detector 2 reg8 b0 watchdog bias sw3 phase detect amp. detect stv0042/stv0056a
11/34 stv0056a channels only one of the selected input audio channels. to allow a very cost ef fective application, each channel uses pll demodulation. neither external complex filter nor ceramic filters are needed. the frequency of the demodulated subcarrier is chosen by a frequency synthesizer which sets the frequency of the internal local oscillator by com- paring its phase with the internally generated ref- erence. when the frequency is reached, the microprocessor switches in the pll and the de- modulationstarts. at any moment the microprocessor can read from the device (watchdog registers) the actual fre- quency to which the pll is locked. it can also ver- ify that a carrier is present at the wanted frequency (by reading amplk status bit) thanks to a syn- chronous amplitude detector, which is also used for the audio input agc. in order to maintain constant amplitude of the re- covered audio regardless of variations between satellites or subcarriers, the pll loop gain may be programmed from 56 values. any frequency deviation can be accommodated (from 30khz till 400khz). two different networks can be permanently con- nected for either 75ms or j17 de-emphasis. if 50ms de-emphasis is required, this can be insert- ed by an internal switch , thus allowing a worldwide application. the stv0056a is intended to be compatible with wegener panda system. two types of audio outputs are provided: one is a fixed 1v rms and the other is a gain controlled 2v rms max. the control range being from +12db to ?26.75db with 1.25db steps.this output can also be muted. a matrix is implemented to feed audio to and from decoders vcr?s and tv?s. noise reduction system and de-emphasis can be inserted or by-passed through bus control. also all the audio outputs are tristate-type (high impedance mode is supported), allowing a simple parallel connections to the scarts (twin tuner ap- plications). others a 22khz tone is generated for lnb control. it is selectable by bus control and available on one of the two pins connected to the external video de- emphasis networks. one general purpose i/o is also available on the stv0056a. by means of the i 2 c bus there is the possibility to drive the ics into a low power consumption mode with active audio and video matrixes. indepen- dently from the main power mode, each individual audio and video output can be driven to high im- pedance mode. table 3. absolute maximum ratings table 4. thermal data symbol parameter value unit v cc v dd supply voltage 15 7.0 v v p tot total power dissipation 900 mw t oper operating ambient temperature 0, +70 c t stg storage temperature ?55, +150 c symbol parameter value unit r th(j-a) thermal resistance junction-ambient max 55 c/w
stv0056a 12/34 electrical characteristics v cc = 12v, v dd = 5v, t a = 25c (unless otherwise specified) table 5. dc and ac electrical characteristics table 6. audio demodulator table 7. automatic noise reduction system symbol parameter test conditions min. typ. max. unit v cc v dd supply voltage 11.4 4.75 12 5.0 12.6 5.25 v v iq cc iq dd supply current all audio and all video outputs activated 55 8 70 15 ma ma iqlp cc iqlp dd supply current at low power m ode all audio and all video outputs are in high impedance mode 27 6 35 9 ma ma symbol parameter test conditions min. typ. max. unit fmin fm subcarrier input level (pin fmin for agc action) vco locked on carrier at 6mhz 560k ? load on amplock pins 180k ? load on det pins 5 500 mv pp deth detector 1 and 2 (amplock pins) (threshold for activating level detector 2) 8mv pp fmin 500mv pp carrier without modulation 2.90 3.10 3.30 v vcomi vco mini frequency v cc : 11.4 to 12.6v, tamb: 0 to 70c 5mhz vcoma vco maxi frequency 10 mhz ap50 1khz audio level at pll output (det pins) 0.5v pp 50khz dev. fm input, coarse deviation set to 50khz (reg. 05 = 36 hex ) 0.6 1 1.35 v pp apa50 1khz audio level at pll output (det pins) 0.5v pp 50khz dev. fm input, coarse and fine settings used 0.92 1 1.08 v pp fmbw fm demodulator bandwidth gain at 12khz versus 1khz 180k ? , 82k ? 22pf on det pins 00.3 1 db dpco digital phase comparator output current (cpump pins) average sink and source current to external capacitor 60 a symbol parameter test conditions min. typ. max. unit lrs output level (pins level) 1v pp on left and right channel 0.9 1 1.1 v pp ldor level detector output resistance (pins pk out) 4.0 5.4 6.8 k ? ndft level detector fall time constant (pins pk out) external 22nf to gnd and 1.2m ? to v ref 26.4 ms ndll bias level (pins pk out) no audio in 2.40 v llcf noise reduction cut-off frequency at low level audio 100mv pp on det pins, external capacitor 330pf (fc pins) 0.85 khz hlcf noise reduction cut-off frequency at high level audio 1v pp on det pins, external capacitor 330pf (fc pins) 7khz
13/34 stv0056a table 8. audio output (p ins vol out r, vol out l) symbol parameter test conditions min. typ. max. unit dcol dc output level 4.8 v aoln audio output level with reg 00 = 1a fm input as for apa50 no de-emphasis, no pre-emphasis no noise reduction 1.5 1.9 2.34 v pp aol50 audio output level with reg 00 = 1a fm input as for apa50 50s de-emphasis, 27kw//2.7nf load no pre-emphasis, no noise reduction 2.0 3.3 4.0 v pp aol75 audio output level with reg 00 = 1a fm input as for apa50 75s de-emphasis, 27k ? //2.7nf load no pre-emphasis, no noise reduction 2.0 3.3 4.0 v pp aol17 audio output level with reg 00 = 1a fm input as for apa50 j17 de-emphasis, 36k ? 4.7k ? 8.2nf load no pre-emphasis, no noise reduction 2.0 3.2 4.0 v pp ama1 audio output attenuation with mute-on. reg 00 = 00 1v pp - 1khz from s2 rtn pins 60 65 db mxat max attenuation before mute. reg 00 = 01 1khz, from s2 rtn pins 32.75 db mxag audio gain. reg 00 = 1f 1khz, from s2 rtn pins 5 6 7 db astp attenuation of each of the 31 steps 1khz 1.25 db thda1 thd with reg 00 = 1a 1v pp -1khz from s2 rtn pins 0.15 % thda2 thd with reg 00 = 1a 2v pp -1khz from s2 rtn pins 0.3 1 % thdfm thd with reg 00 = 1a fm input as for apa50 75s de-emphasis, anrs on 0.3 1 % acs audio channel separation 1v pp -1khz on s2 rtn pins 60 74 db acsfm audio channel separation at 1khz ?0.5 v pp - 50khz deviation fm input on one channel ?0.5v pp no deviation fm input on the other channel ? reg 05 = 36 hex ? 75ms de-emphasis, no anrs 60 db snfm signal to noise ratio fm input as for apa50, 75s de-emphasis, no anrs, unweighted 56 snfmnr signal to noise ratio fm input as for apa50 75s de-emphasis, anrs on, unweighted 69 z out l z out h audio output impedance low impedance mode high impedance mode 30 18 44 55 ? k ?
stv0056a 14/34 table 9. auxiliary audio output (pins s2 out r, s2 out l, s3 out r, s3 out l) table 10. i/o table 11. reset symbol parameter test conditions min. typ. max. unit dcolao dc output level aux. input pins open circuit 4.8 v aolns audio output level on s2 and s3 fm input as for apa50 no de-emphasis, no pre-emphasis no noise reduction 1.55 2 2.42 v pp aol50s audio output level on s2 and s3 fm input as for apa50 50ms de- emphasis, 27k ? //2.7nf load no pre-emphasis, no noise reduction 2.0 3.4 4.0 v pp aol75s audio output level on s2 and s3 fm input as for apa50 75ms de- emphasis, 27k ? //2.7nf load no pre-emphasis, no noise reduction 2.0 3.4 4.0 v pp aol17s audio output level on s2 and s3 fm input as for apa50 j17 de- emphasis, 36k ? 4.7k ? 8.2nf load no pre-emphasis, no noise reduction 2.0 3.3 4.0 v pp agao s2 to s3 audio gain and s3 to s2 audio gain 1khz ?1 0 +1 db thda02 thd on s2, input in s3 2v pp - 1khz from aux input pins 0.04 0.2 % thdaofm thd on s2 or s3 fm input as for apa50 75s de-emphasis, no anrs 0.3 1 % z out l z out h audio output impedance low impedance mode high impedance mode 30 60 44 100 55 ? k ? symbol parameter test conditions min. typ. max. unit v il v ih low level input high level input 2.4 0.8 v v v ol v oh low level output high level output i sink = 2ma i source = 2ma 3.2 0.2 4.6 0.4 v v lnb t tone frequency 22.2 22.2 22.2 khz lnb d tone signal duty cycle no load connected on i/o 49 50 51 % symbol parameter test conditions min. typ. max. unit rtccu end of reset threshold for v cc v dd = 5v, v cc going up 8.7 v rtccd start of reset threshold for v cc v dd = 5v, v cc going down 7.9 v rtddu end of reset threshold for v dd v cc = 12v, v dd going up 3.8 v rtddd start of reset threshold for v dd v cc = 12v, v dd going down 3.5 v
15/34 stv0056a table 12. composite signal processing table 13. clamp stages (pins clamp in, s1, s2, s3 vid rtn) table 14. video matrix symbol parameter test conditions min. typ. max. unit vidc vid in external load current < 1a 2.25 2.45 2.65 v zvi vid in input impedance 7 11 14 kw deodc dc output level (pins videem) 2.25 2.45 2.65 v deomx max ac level before clipping (pins videem) gv = 0db, reg 01 = 00 2 0 v pp dgv gain error vs gv @100khz gv = 0 to 12.7db, reg 01 = 00 3f ?0.5 ?1 0.5 db invg inverter gain de-emphasis amplifier mounted in unity gain, normal video selected -0.9 0 ?1.1 db visog video input to scart outputs gain @ ? 3db with gv = 0db, reg 01 = 00 ?1 1 mhz debw bandwidth for 1v pp input measured on pins videem gv = 0db, 1v pp cvbs + 0.5v pp 10 % dfg differential gain on sync pulses measured on pins videem 25hz sawtooth (input : vid in) 1 db itmod intermodulation of fm subcarriers with chroma subcarrier 7.02 and 7.2mhz sub-carriers, 12.2db lower than chroma -60 v symbol parameter test conditions min. typ. max. unit iskc clamp input sink current v in = 3v 0.5 1 1.5 a iscc clamp input source current v in = 2v 40 50 60 a symbol parameter test conditions min. typ. max. unit xtk output level on any output when 1v pp cvbs input is selected for any other output @ 5mhz -60 db bfg output buffer gain (pins s1 vid out, s2 vid out, s2 vid out) @ 100khz 1.87 2 2.13 dcolvh dc output level high impedance mode 0 0.2 v z out hv video output impedance high impedance mode 16 23 30 k ? vcl sync tip level on selected outputs (pins s1 vid out, s2 vid out) 1v pp cvbs through 10nf on input 1.05 1.3 1.55 v vcl s3 sync tip level at s3 vid out with black level adjust register 4 b6 b7 00 01 10 11 1.36 1.52 1.67 1.84 v v v v
stv0056a 16/34 pin internal circuitry s1 vid rtn, s2 vid rtn, s3 vid rtn, clamp in 50ma source is active only when vidin < 2.7v. figure 9. s3 vid out i black level is i 2 c programmable from source 16ma to sink 33a equivalent to an offset voltage of ?150mv to +300mv. the 60 ? collector resistor is for short cct. protec- tion. figure 10. s1 vid out, s2 vid out same as above but with no black level adjustment. figure 11. uncl deem same as above but with no black level adjustment and slightly different gain. figure 12. videem1 ron of the transistor gate is 910k ? . figure 13. s1 vid rtn s2 vid rtn s3 vid rtn clamp in 50a 1a 10k ? v dd 9v gnd 0v 1 1 vid mux 10k ? 16.7k ? i black level 25k ? 60 ? 2.3ma gnd 0v gnd 0v s3 vid out 4 v cc 12v v ref 2.4v + - vid mux 10k ? 20k ? 20k ? 60 ? 2.3ma gnd 0v gnd 0v s1 vid out s2 vid out 4 v cc 12v v ref 2.4v + - in 10k ? 16.7k ? 25k ? 60k ? 2.3ma gnd 0v gnd 0v uncl deem 4 v cc 12v v ref 2.4v + - 6/2 10/2 125a videem1 1
17/34 stv0056a videem2 / 22khz ron of the transistor gate is 910k ? . figure 14. vid in figure 15. pk outr, pk out l figure 16. fc l, fc r ivar is controlled by the peak det audio level max. 15a (1v pp audio). figure 17. vol out r, vol out l audio output with volume and scart driver with +12db of gain for up to 2v rms . the opamp has a push-pull output stage. figure 18. s2 out l, s2 out r, s3 out l, s3 out r same as above but with gain fixed at +6db. figure 19. 6/2 10/2 100/2 v dd 5v 22khz 60/2 125a videem2/22khz 1 85a 10k ? 6.5k ? 0.5pf gnd 0v v ref 2.4v vid in 1 + 5k ? audio peak detector 1 1 v dd 9v 3.4v pk out r pk out l clamp + - + - 1 1 v dd 9v fc l fc r ivar vol out r vol out l 4.8v 30k ? 30k ? 15k ? gnd 0v audio 2.4v bias + - s2 out l s2 out r s3 out l s3 out r 20k ? 20k ? gnd 0v audio 2.4v bias + -
stv0056a 18/34 s2 rtn l, s2 rtn r, s3 rtn l, s3 rtn r 4.8v bias voltage is the same as the bias level on the audio outputs. figure 20. fm in the other input for each channel is internally bi- ased in the same way via 10k ? to the 2.4v v ref . figure 21. i ref the optimum value if i ref is 50ma 2% so an ex- ternal resistor of 47.5k ? 1% is required. figure 22. i/o/ 22khz the input is ttl compatible. the output is tri-stateable. figure 23. scl this is the input to a schmitt input buffer made with a cmos amplifier. figure 24. sda input same as above. output pull down only: relies on external resistor for pull-up. figure 25. 50a 25k ? 4.8v 1 s2 rtn l s2 rtn r s3 rtn l s3 rtn r 50a 50a left channel right channel 10k ? 10k ? 2.4v fm in 1 1 i ref 2.4v 1 + - 180/2 205 ? esd i/o/22khz iic reg 100/2 10/2 91/2 mux 22khz 205 ? esd 24/4 scl 600/2 gnd 0v 205 ? esd 24/4 sda
19/34 stv0056a j17 l, j17 r, u75 l, u75 r i1 ? i2 = 2 x audio / 18k ? . eg 1v pp audio: 55a. the are internal switches to match the audio level of the different standards. figure 26. ha pull-down current for sdip42. input with cmos levels. figure 27. xtl figure 28. cpump l, cpump r an offset on the pll loop filter will cause an offset in the two 1ma currents that will prevent the pll from drifting-off frequency. figure 29. det l, det r i2 ? i1 = f (phase error). figure 30. amplk l, amplk r, agc l, agc r i2 and i1 from the amplitude detecting mixer. figure 31. j17 l j17 r u75 l u75 r i1 i2 205 ? esd ha gnd 0v 25/2 10/2 150a xtl 3 22 3 460 ? 460 ? 750a gnd 0v 5pf 750a 500a 100a 100a cpump l cpump r 1a 1a dig synth loop filter tracking vco input + - det l det r i1 i2 amplk l amplk r agc l agc r i2 i1 2 10k ? 160a 5a v ref 2.4v to vca
stv0056a 20/34 v ref the 400a source is off during stand-by mode. figure 32. level l, level r figure 33. pk in l, pk in r v 12v doubled bonded (two bond wires and two pads for one package pin): ? one pad is connected to all of the 12v esd and video guard rings. ? the second pad is connected to power up the video block. v gnd doubled bonded: ? one pad is connected to power-up all of the video mux and i/o. ? the second pad is only as a low noise gnd for the video input. vdd 5v,gnd 5v connected to xtl oscillato r and the bulk of the cmos logic and 5v esd. a gnd doubled bonded: ? one pad connected to the left vco, dividers, mixers and guard ring. the guard connection is star connected directly to the pad. ? the second pad is connected to both agc amps and the deemphasis amplifiers, frequency synthesis and fm deviation selection circuit for both channels. a 12v doubled bonded:e pad connected to the esd and guard ring. ? the second pad is connected to the main power for all of the audio parts. a gnd r doubled bonded: ? one pad connected to the right vco, dividers, mixers and guard ring. the guard connection is star connected directly to the pad. ? the second pad is connected to the bias block, audio noise reduction, volume, mux and esd. a third bond wire on this pin is connected directly to the die pad (substrate). figure 34. vbg 1.2v 4 10k ? v ref (2.4v) 10k ? 400a gnd 0v + - v ref (2.4v) sw audio 49k ? 49k ? 49k ? 100a level r level l 1 + - 67k ? 100a to peak det 1 v ref 2.4v pk in r pk in l + - vpp bip 10vpl vmm v gnd gnd 5v dzpn1 dzpn1 dzpn1 a gnd l a 12v bip 12 v a gnd r substrate v 12v video pads v dd 5v digital pads 205 ? audio pads + -
21/34 stv0056a i 2 c protocol 1) writing to the chip s -start condition p -stop condition chip addr - 7 bits. programmable 06h or 46h (stv0056a only) with pin ha. w -write/read bit is the 8th bit of the chip address. a -acknowledge after receiving 8 bits of data/address. reg addr address of register to be written to, 8 bits of which bits 3, 4, 5, 6 & 7 are ?x? or don?t care ie only the first 3 bits are used . data 8 bits of data being written to the register. all 8 bits must be written to at the same time. reg addr/a/data/a can be repeated, the write process can continue until terminated with a stop condition. if the reg addr is higher than 07 then iic protocol will still be met (ie an a generated). table 15. example 2) reading from the chip when reading, there is an auto-increment feature. this means any read command always starts by read- ing reg 8 and will continue to read th e following registers in order afte r each acknowledge or until there is no acknowledge or a stop. this function is cyclic th at is it will read the same set of registers without re- addressing the chip. there are two modes of operation as set by writing to bit 7 of register 0. read 3 reg- isters in a cyclic fashion or all 5 regi sters in a cyclic fashion. note only the last 5 of the 11 registers can be read. reg0 bit 7 = l ? start / chip add / r / a/ reg 8 / a / reg 9 / a/ reg 0a/ a/ reg 8 / a/ reg 9 / a / reg 0a /... / p / reg0 bit 7 = h ? start / chip add / r / a/ reg 8 / a / reg 9 / a/ reg 0a / a / reg 7 / a / reg 6 / a / reg 8 / a/ reg 9 / a / reg 0a / a/ reg 7 / a/ reg 6 / ... / p / s 06 w a 00 a 55 a 01 a 8f ............ a p
stv0056a 22/34 control registers reg 0 write only bit (default 00 hex ) 0 l select 5 bits audio volume control 00h = mute 1 l select 5 bits audio volume control 01h = -26.75db 2 l select 5 bits audio volume control ::: : : 3 l select 5 bits audio volume control 1.25db steps up to 4 l select 5 bits audio volume control 1fh = +12db 5 l audio mux switch k4 - anrs i/p select (l = pll) 6 l audio mux switch k3 - anrsselect (l = no anrs, h = anrs) 7 l l = read 3 registers, h = read 5 registers reg 1 write only bit (default 00 hex ) 0 l select video gain bits 1 l select video gain bits 00h = 0db 2 l select video gain bits 01h = +0.202db 3 l select video gain bits 02h = +0.404db 4 l select video gain bits n = + 0.202 db * n 5 l select video gain bits 3fh = + 12.73 db 6 l selected video invert (h = inverted, l = non inverted) 7 l video de-emphasis 1 / video de-emphasis 2 (l: vid de-em 1) reg 2 write only bit (default f7 hex ) 0 h select video source for scart 1 o/p 1 h select video source for scart 1 o/p 2 h select video source for scart 1 o/p 3 l select 4.000mhz or 8.000mhz clock speed (l = 8mhz) 4 h select audio source for volume output (switch k1) 5 h select audio source for volume output (switch k1) 6 h select left/right/stereo for volume output 7 h select left/right/stereo for volume output reg 3 write only bit (default f7 hex ) 0 h select video source for scart 2 o/p 1 h select video source for scart 2 o/p 2 h select video source for scart 2 o/p 3 l video de-emphasis 2 / 22khz (h: 22khz) 4 h select audio source for scart 2 output (switch k5) 5 h select audio source for scart 2 output (switch k5) 6 h audio de-emphasis select (switch k2) 7 h audio de-emphasis select (switch k2) reg 4 write only bit (default bf hex ) 0 h select source for video decoder o/p 1 h select source for video decoder o/p 2 h select source for video decoder o/p 3 h stand-by or low power mode (h = low power) 4 h select audio source for scart 3 output (switch k6) 5 h select audio source for scart 3 output (switch k6) 6 l black level adjust on scart 3 video 7 h black level adjust on scart 3 video
23/34 stv0056a reg 5 write only bit (default b5 hex ) 0 h fm deviation selection -- default value for 50khz modulation 1 l fm deviation selection 2 h fm deviation selection 3 l fm deviation selection 4 h fm deviation selection 5 h fm deviation selection (l = double the fm deviation) 6 l select 22khz for i/o (pin 29 / stv0056a) 7 h select tp50a (h) or i/o (pin 29 / stv0056a). tp50a for test only. reg 6 write/read bit (default 86 hex ) 0 l status of i/o 1 h select data direction of i/o 1 (h = output) 2 h select frequency synthesizer 1 off/on (l = off) 3 l select frequency synthesizer 2 off/on (l = off) 4 l select rf source (l = off) to fm det 1 5 l select rf source (l = off) to fm det 2 6 l select frequency for pll synthesizer - lsb (bit 0) of 10-bit value 7 h select frequency for pll synthesizer - bit 1 of 10-bit value reg 7write/read bit (default af hex ) 0 h select frequency for pll synthesizer - bit 2 of 10-bit value 1 h select frequency for pll synthesizer 2 h select frequency for pll synthesizer 3 h select frequency for pll synthesizer 4 l select frequency for pll synthesizer 5 h select frequency for pll synthesizer 6 l select frequency for pll synthesizer 7 h select frequency for pll synthesizer - bit 9, msb (10th bit) of 10-bit value reg 8 read only bit 0 subcarrier detection (det 1) (l = no subcarrier) 1 not used 2 read frequency of watchdog 1 - lsb (bit 0) of 10-bit value 3 read frequency of watchdog 1 - bit 1 of 10-bit value 4 subcarrier detection (det 2) (l = no subcarrier) 5 not used 6 read frequency of watchdog 2 - bit 0 of 10-bit value 7 read frequency of watchdog 2 - bit 1 of 10-bit value reg 9 read only bit (default af hex ) 0 read frequency of watchdog 1 - bit 2 of 10-bit value 1 read frequency of watchdog 1 2 read frequency of watchdog 1 3 read frequency of watchdog 1 4 read frequency of watchdog 1 5 read frequency of watchdog 1 6 read frequency of watchdog 1 7 read frequency of watchdog 1 - bit 9, msb (10th bit) of 10-bit
stv0056a 24/34 reg 0a read only bit 0 read frequency of watchdog 2 - bit 2 of 10-bit value 1 read frequency of watchdog 2 2 read frequency of watchdog 2 3 read frequency of watchdog 2 4 read frequency of watchdog 2 5 read frequency of watchdog 2 6 read frequency of watchdog 2 7 read frequency of watchdog 2 - bit 9, msb (10th bit) of 10-bit video mux truth tables register 2 <0:2> ? scart 1 video output control register 3 <0:2> ? scart 2 video output control register 4 <0:2> ? scart 3 decoder output control the truth table for the three scart outputs are the same. table 16. audio mux truth tables register 2/3/4 video output bit<2> 0 0 0 0 1 1 1 1 bit<1> 0 0 1 1 0 0 1 1 bit<0> 0 1 0 1 0 1 0 1 baseband video de-emphasized video normal video scart 3 return scart 2 return scart 1 return nothing selected high z or low power (default) register 4 black level adjust on scart 3 bit<7> 0 1 0 1 bit<6> 0 0 1 1 ?150mv 0 (default) +150mv +300mv register 2 switch k1/audio source selection for volume output bit<5> 0 1 0 1 bit<4> 0 0 1 1 a c b - volume output audio de-emphasis (k2 switch o/p) scart 2 return scart 3 return high z or low power (default) register 3 switch k2/audio de-emphasis bit<7> 0 1 0 1 bit<6> 0 0 1 1 a c b b audio de-emphasis no de-emphasis j17 50s 75s (default)
25/34 stv0056a register 0 switch k3 & k4 bit <6> 0 1 x x bit <5> x x 0 1 a b a b anrs i/o select noise reduction off noise reduction on (default) i/p = pll i/p = scart 3 return register 3 switch k5/audio source selection for scart 2 bit <5> 0 1 0 1 bit <4> 0 0 1 1 c a b - aux audio output pll output scart 3 return audio de-emphasis (k2 switch o/p) high z or low power state (default) register 4 switch k6/audio source selection for scart 3 bit <5> 0 1 0 1 bit <4> 0 0 1 1 a c b - audio decoder output pll output audio de-emphasis (k2 switch o/p) scart 2 return high z or low power state (default) register 2 left / right / stereo on volume output bit <7> 0 1 1 bit <6> 0 0 1 mono left / channel 1 mono right / channel 2 stereo left & right (default)
stv0056a 26/34 table 17. register 5: fm deviation selection 43210 selected nominal carrier modulation bit 5 = 0 bit 5 = 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 do not use do not use do not use cal. set. (2v) 592khz 534khz 484khz 436khz 396khz 358khz 322khz 292khz 266khz 240khz 218khz 196khz 179khz 161khz 146khz 122khz 120khz 109khz 98khz 89khz 78khz 71khz 65khz 58khz 53khz 48.6khz 43.8khz 39.6khz cal: do not use = 0.3373v offset on vco cal: do not use = 0.3053v offset on vco cal: do not use = 0.2763v offset on vco calibration setting (1 v offset on vco) 296khz modulation 267khz modulation 242khz 218khz 198khz 179khz 161khz 146khz 133khz 120khz 109khz 98.3khz 89.7khz 80.9khz 73.1khz 66.0khz 60.0khz 54.4khz = default power up state 49.1khz 44.3khz 39.8khz 35.9khz 32.4khz 29.1khz 26.7khz 24.3khz 21.9khz 19.7khz register 1 bit <7> register 3 bit <3> video de-emphasis/22khz 0 0 1 1 0 1 0 1 de-emphasis 1 (default) de-emphasis 1 + 22khz de-emphasis 2 de-emphasis 2 register 5 digital i/o (stv0056a pin 29) bit <7> 0 0 1 1 bit <6> 0 1 0 1 i/o (refer to register 6 bit <0> bit <1>) 22khz do not use (for test only) (default) 22khz
27/34 stv0056a fm demodulation software routine with the stv0056a circuit, for each channel, three steps are required to achieve a fm demodulation: ? 1st step: to set the demodulation parameters: fm deviation selection, subcarrier frequency selection. ? 2nd step: to implement a waiting loop to check the actual vco frequency. ? 3rd step: to close the demodulation phase locked loop (pll). referring to the fm demodulation block diagram, the frequency synthesis block is common to both channels (left and right); consequently two com- plete sequence shave to be done one after the other when demodulating stereo pairs. detailed description conventions: ? r = stands for register ? b = stands for bit example : r05 b2 = register 05, bit 2 for clarity, the explanations are based on the fol- lowing example: stereo pair 7.02mhz/l 7.20mhz/ r, deviation 50khz max. 1st step (left): setting the demodulation parameters a. the fm deviation is sele cted by loading r5 with the appropriate value (see r5 truth table). nb: very wide deviations (up to 592khz) can be accommodated when r5 b5 is low. corresponding bandwidth can be calculated as follows: bw 2 (fm deviation + audio bandwidth) bw 2 (value given in table + audio bandwidth) in the example: r5 bits 76543210 xx110110 b. the subcarrier frequency is selected by launch- ing a frequency synthesis (the vco is driven to the wanted frequency). this operation requires two actions: ? to connect the vco to the frequency synthesis loop. refering to the fmblock diagram: sw4 closed ? r6 b2 = h sw3 to bias ? r6 b4 = l sw2 to bias ? r6 b3 = l sw1 opened ? r6 b5 = l ? to load r7 and r6 b6 b7 with the value corresponding to the left channel frequency. this 10 bits value is calculated as follows: subcarrier frequency = coded value x 10khz (10khz is the minimum step of the frequency synthesis function) considering that the tunning range is comprised between5 to 10mhz, the coded valueis a number between 500 and 1000 (2 10 = 1024) then 10 bits are required. example : 7.02mhz = 702 x 10khz 702 ? 1010 1111 10 ? af + 10 r7 is loaded with af and r6 b6: l, r6 b7: h. table 18 gives the setting for the most common subcarrier frequencies. table 18. frequency synthesis register setting for the most common subcarrier frequencies subcarrier frequency (mhz) register 7 (hex) register 6 bit 7 bit 6 5.58 8b 1 0 5.76 90 0 0 5.8 91 0 0 5.94 94 1 0 6.2 9b 0 0 6.3 9d 1 0 6.4 a0 0 0 6.48 a2 0 0 6.5 a2 1 0 6.6 a5 0 0 6.65 a6 0 1 6.8 aa 0 0 6.85 ab 0 1 7.02 af 1 0 7.20 b4 0 0 7.25 b5 0 1 7.38 b8 1 0 7.56 bd 0 0 7.74 c1 1 0 7.85 c4 0 1 7.92 c6 0 0 8.2 cd 0 0 8.65 d8 0 1
stv0056a 28/34 2nd step (left): vco frequencychecking (vco) this second step is actua lly a waiting loop in which the actual running frequency of the vco is mea- sured. to exit of this loop is allowed when: subcarrier frequency - 10khz measured frequency sub- carrier frequency + 10khz ( 10khz is the maxi- mum dispersion of the frequency synthesis function). in practice, r8 b2 b3 and r9 are read and com- pared to the value loaded in r6 b6 b7 and r7 1 bit. note: the duration of this step depends on how large is frequency difference between the start frequency and the targeted frequency. typically: ? the rate of change of the vco frequency is about 3.75mhz/s (c pump = 10f) ? in addition to this settling time, 100ms must be added to take into account the sampling period of the watchdog. 3rd step (left) the fmdemodulationcan bestarted byconnecting the vco to the phase locked loop (pll). in practice: ? sw3 closed ? r6 b4 = h ? sw4 opened ? r6 b2 = l after this sequence of 3 steps for left channel, a similar sequence is needed for the right channel. note: in the sequence for the right, there is no need to again select the fm deviation (once is enough for the pair). general remark before to enable the demodulated signal to the au- dio output, it is recommanded to keep the muting and to check whether a subcarrier is present at the wanted frequency. such an information is avail- able in r8 b0 and r8 b4 which can be read. two different strategies can be adopted when en- abling the output: ? either both left and right demodulated signals are simultaneously authorized when both channel are ready. ? or while the right channe l sequenceis running, the already ready left signal is sent to the left and right outputs and the real stereo sound l/r is output when both channels are ready. this second option gives sound a few hundreds of ms before the first one.
29/34 stv0056a figure 35. typical application (3 sc arts, pal/secam europe apllication) broadband video processor audio stereo matrix two-channel fm demodulator 22khz generator i 2 c decoder and deemphasis noise reduction video matrix stv0056a c64 1.5nf r58 43k ? 1 2 3 16 17 18 19 20 11 12 13 14 15 21 40 41 47 48 49 42 43 44 45 46 50 56 39 38 37 36 35 r57 24k ? c63 220nf r54 3.3k ? c62 8.2nf r55 1.5k ? c61 1.5nf q4 bc557 r56 10k ? v cca r53 43k ? c60 1.5nf c58 100nf r50 47.5k ? 1% c50 10 f 16v + r37 560k ? c45 100nf v cca r51 560k ? r40 180k ? c47 22pf c48 22pf r41 82k ? c46 2.7nf r39 27k ? c40 470 f 16v + c43 100nf r36 560k ? c42 100nf c39 2.7nf r34 27k ? r33 180k ? c38 22pf c37 22pf r32 82k ? c41 10 f 16v + v dd c29 22pf 1 2 3 4 c66 47pf j10 5v sda scl gnd 1 1 i/o clock input j9 j8 1 1 5v gnd j12 j11 l1 22 h + c31 220 f 16v c30 100nf v dd 1 1 12v gnd j14 j13 l2 22 h + c33 220 f 16v c32 100nf v ccv + c35 220 f 16v c34 100nf v cca v ccv c56 100nf c23 8.2nf c24 27pf r17 470 ? r18 1k ? l4 47 h c25 100pf r48 75 ? c26 10 f 16v j7 tuner input c12 100pf r9 5.1k ? + c13 10 f 16v r11 1.5k ? r10 10k ? c5 2.2 f vcr scart 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 j2 v ccv q1 bc547 tv scart 6 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 j1 j6 r j5 l j4 v r2 68k ? r3 470 ? c2 2.2 f c3 2.2 f jp12 v ccv q2 bc547 r4 470 ? r5 68 ? c6 2.2 f c8 2.2 f c7 2.2 f c11 8.2nf r16 1k ? 3 2 1 tdk filter sel5618 r6 75 ? c4 220nf sel56185mhz lpf made by tdk / japan 55 r116 10k ? q103 bc557 r115 1.5k ? c113 1.5nf c114 8.2nf r117 24k ? r114 3.3k ? 54 53 c115 220nf 52 c112 100nf r113 560k ? 51 34 33 32 r106 36k ? c108 8.2nf r107 4.7k ? r105 36k ? c107 8.2nf r104 4.7k ? 31 30 29 c65 47pf 4 5 8 9 c100 220nf r100 75 ? 10 v ccv r101 470 ? q101 bc547 c102 2.2 f decoder scart 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 j3 c105 2.2 f c104 2.2 f c103 2.2 f r102 75 ? c101 220nf r103 68 ? 22 23 24 25 26 27 28 r15 1k ? 4mhz or 8mhz crystal c65 100nf r59 1.2m ? r60 1.2m ? c66 100nf
stv0056a 30/34 twin tuner application easy parallel connection of the outputs to the carts without any additional switching hardware. this configuration is possible due to the high im- pedance mode that can be selected for each audio and video outputs. figure 36. twin tuner application 7 8 9 32 27-28 12-14 6-10 7 8 9 32 audio video 2 audio video 2 audio video 2 5v 27-28 12-14 6-10 tuner 1 tuner 2 i 2 c bus s t v 0 0 5 6 a s t v 0 0 5 6 a decoder scart vcr scart tv scart
31/34 stv0056a part numbering table 19. order codes part number package temperature range stv0056a shrink56 0 to 70c
stv0056a 32/34 package mechanical table 20. shrink56 plastic - mechanical data figure 37. shrink56 plastic - package dimensions note: drawing is not to scale symbol millimeters inches min typ max min typ max a 5.08 0.200 a1 0.51 0.020 b 0.35 0.59 0.014 0.023 b1 0.75 1.42 0.030 0.056 c 0.20 0.36 0.008 0.014 d 52.12 2.052 d1 ? ? ? ? ? ? e 18.54 0.730 e1 13.72 0.540 k1 ? ? ? ? ? ? k2 ? ? ? ? ? ? l 2.54 3.81 0.100 0.150 e1 1.78 0.070 number of pins n 56 1 n n/2 b b1 e1 d d1 a1 l a k1 k2 e1 e c
33/34 stv0056a revision history table 21. revision history date revision description of changes september-1996 1 first issue 9-june-2004 2 stylesheet update. no content change.
stv0056a 34/34 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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